Professional homepage of Thomas Ferrère

Hardware Engineer.



Short Bio

From 2016 to 2019, I was a postdoctoral researcher at IST Austria, Klosterneuburg, Austria in the group of Tom Henzinger. Previously, I was a PhD student at Verimag, University of Grenoble, France under the supervision of Oded Maler, and in collaboration with Mentor Graphics corporation under the CIFRE scheme. My research is in the verification and validation of embedded systems, with contributions in logic monitoring, pattern matching, fault localization, and automata theory. I hold a master's in mathematical logic from the University of Paris Diderot and an engineer diploma in mathematical modelling from the University of Clermont-ferrand, France.

Scientific Events

PhD Thesis

Assertions and Measurements for Mixed-Signal Simulation, University of Grenoble, 2016.


Arranged by topic and in chronological order. See also my pages at DBLP and Google Scholar. Copyright belongs to respective publishers.